1. Field of the Invention
This invention relates generally to semiconductors and, more particularly, to trench memory devices and a method for manufacturing same.
2. Description of the Related Art
In trench memory, retention of an electric charge in a cell capacitor is greatly influenced by various leakage mechanisms. Trench memory devices or structures are subject to vertical parasitic leakage that degrades charge or data retention. As shown in FIG. 1, a vertical parasitic transistor is formed in a contemporary trench memory structure where the N+ buried strap is the drain, the N+ buried plate is the source, the N+ trench poly is the gate and the collar oxide is the gate dielectric. Vertical parasitic leakage current is generated due to the sub-threshold current of the vertical parasitic transistor, degrading the charge retention.
The resulting vertical parasitic leakage current can be suppressed through increased p-well doping. However, increasing p-well doping leads to other problems, such as elevated junction leakage and depressed write-back current.
In U.S. Pat. No. 6,818,534, it is suggested to utilize a fully doped collar in trench DRAM to improve leakage performance. As shown in FIG. 2, a fully boron-doped collar is utilized. However, the boron in the collar counter-dopes arsenic-doped N+ poly, causing high poly resistance. Additionally, the fully boron-doped collar is left exposed during subsequent high-temperature processes, such as, for example, the STI process. These high-temperature processes cause boron contamination and undesired auto-doping in the active area. The closeness of the heavily doped P-well also disturbs the characteristics of the array transistor.
Accordingly, there is a need for trench memory that reduces or suppresses vertical parasitic leakage. There is a further need for a process of manufacturing such trench memory structures or devices.